#ifndef  __ADF4351_REGS_H__
#define __ADF4351_REGS_H__

/* Registers */
#define ADF4351_REG0    0
#define ADF4351_REG1    1
#define ADF4351_REG2    2
#define ADF4351_REG3    3
#define ADF4351_REG4    4
#define ADF4351_REG5    5

/* REG0 Bit Definitions */
#define ADF4351_REG0_FRACT(x)                    (((x) & 0xFFF) << 3)
#define ADF4351_REG0_INT(x)                      (((x) & 0xFFFF) << 15)

/* REG1 Bit Definitions */
#define ADF4351_REG1_MOD(x)                      (((x) & 0xFFF) << 3)
#define ADF4351_REG1_PHASE(x)                    (((x) & 0xFFF) << 15)
#define ADF4351_REG1_PRESCALER                   (1 << 27)
#define ADF4351_REG1_PHA_ADJ                     (1 << 28)

/* REG2 Bit Definitions */
#define ADF4351_REG2_COUNTER_RESET_EN            (1 << 3)
#define ADF4351_REG2_CP_THREESTATE_EN            (1 << 4)
#define ADF4351_REG2_POWER_DOWN_EN               (1 << 5)
#define ADF4351_REG2_PD_POLARITY_POS             (1 << 6)
#define ADF4351_REG2_LDP_6ns                     (1 << 7)
#define ADF4351_REG2_LDP_10ns                    (0 << 7)
#define ADF4351_REG2_LDF_FRACT_N                 (0 << 8)
#define ADF4351_REG2_LDF_INT_N                   (1 << 8)
#define ADF4351_REG2_CHARGE_PUMP_CURR_uA(x)     (((((x)-312) / 312) & 0xF) << 9)
#define ADF4351_REG2_DOUBLE_BUFF_EN              (1 << 13)
#define ADF4351_REG2_10BIT_R_CNT(x)              ((x) << 14)
#define ADF4351_REG2_RDIV2_EN                    (1 << 24)
#define ADF4351_REG2_RMULT2_EN                   (1 << 25)
#define ADF4351_REG2_MUXOUT(x)                   ((x) << 26)
#define ADF4351_REG2_NOISE_MODE(x)               ((x) << 29)

/* REG3 Bit Definitions */
#define ADF4351_REG3_12BIT_CLKDIV(x)             ((x) << 3)
#define ADF4351_REG3_12BIT_CLKDIV_MODE(x)        ((x) << 16)
#define ADF4351_REG3_12BIT_CSR_EN                (1 << 18)
#define ADF4351_REG3_CHARGE_CANCELLATION_EN      (1 << 21)
#define ADF4351_REG3_ANTI_BACKLASH_3ns_EN        (1 << 22)
#define ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH    (1 << 23)

/* REG4 Bit Definitions */
#define ADF4351_REG4_OUTPUT_PWR(x)               ((x) << 3)
#define ADF4351_REG4_RF_OUT_EN                   (1 << 5)
#define ADF4351_REG4_AUX_OUTPUT_PWR(x)           ((x) << 6)
#define ADF4351_REG4_AUX_OUTPUT_EN               (1 << 8)
#define ADF4351_REG4_AUX_OUTPUT_FUND             (1 << 9)
#define ADF4351_REG4_AUX_OUTPUT_DIV              (0 << 9)
#define ADF4351_REG4_MUTE_TILL_LOCK_EN           (1 << 10)
#define ADF4351_REG4_VCO_PWRDOWN_EN              (1 << 11)
#define ADF4351_REG4_8BIT_BAND_SEL_CLKDIV(x)     ((x) << 12)
#define ADF4351_REG4_RF_DIV_SEL(x)               ((x) << 20)
#define ADF4351_REG4_FEEDBACK_DIVIDED            (0 << 23)
#define ADF4351_REG4_FEEDBACK_FUND               (1 << 23)

/* REG5 Bit Definitions */
#define ADF4351_REG5_LD_PIN_MODE_LOW             (0 << 22)
#define ADF4351_REG5_LD_PIN_MODE_DIGITAL         (1 << 22)
#define ADF4351_REG5_LD_PIN_MODE_HIGH            (3 << 22)

/* Specifications */
#define ADF4351_MAX_OUT_FREQ        4400000000ULL /* Hz */
#define ADF4351_MIN_OUT_FREQ        34375000 /* Hz */
#define ADF4351_MIN_VCO_FREQ        2200000000ULL /* Hz */
#define ADF4351_MAX_FREQ_45_PRESC   3000000000ULL /* Hz */
#define ADF4351_MAX_FREQ_PFD        32000000 /* Hz */
#define ADF4351_MAX_BANDSEL_CLK     125000 /* Hz */
#define ADF4351_MAX_FREQ_REFIN      250000000 /* Hz */
#define ADF4351_MAX_MODULUS         4095
#define ADF4351_MAX_R_CNT           1023

#endif
